Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys

ABSTRACT

This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

BACKGROUND

1. Field

The invention relates in general to integrated circuits and devices, inparticular to MOS transistors and Junction Field Effect Transistors(JFETs) and circuits.

2. Description of Related Art

Very Large Scale Integrated Circuits are being scaled to smallerdimensions to gain greater packing density and faster speed in acontinuation of the trend of the past thirty years. Currently, CMOStechnology is being manufactured with sub-100 nanometer (nm) minimumdimensions in 2005. Scaling CMOS with the minimum line width below 100nm presents numerous problems to designers of integrated circuits. A fewof the problems of the scaled CMOS transistors below 100 nm arehighlighted below;

-   -   1. Power dissipation in CMOS is a big problem due to the high        switching load caused by the increase in gate capacitance per        unit area as the thickness of the gate dielectric is scaled.    -   2. The thickness of the gate dielectric used in the MOS        transistor has been scaled down to less than 20 angstroms.        Thinning of the gate dielectric has resulted in a significant        amount of current through the gate dielectric as voltage is        applied to the gate electrode. This current is termed the gate        leakage.    -   3. The transistors conduct a finite current between the drain        and source even when the gate voltage is reduced to zero. This        current is termed the source drain leakage.    -   4. The result of the effects described above is CMOS circuits        which conduct a significant amount of current even when there is        no activity (static current); this undermines a key advantage of        CMOS. Because of the static current, the static power, or the        power dissipated by the CMOS chip when there is no activity, has        become quite large, and at temperatures close to 100 degrees        centigrade, the static power dissipation can become nearly equal        to the dynamic power dissipation in CMOS circuits. As the CMOS        technology is scaled to 65 nm, the problem of leakage is        becoming more severe. This trend continues as the technology is        scaled further to line widths of 45 nm and below.    -   5. The lateral scaling of CMOS design rules has not been        accompanied by vertical scaling of feature sizes, resulting in        three dimensional structures with extreme aspect ratios. For        instance, the height of the polysilicon gate has decreased only        50% while the lateral dimension of the polysilicon gate has been        reduced by over 90%. Dimensions of the “spacer” (a component of        a CMOS transistor which separates the gate from the heavily        doped source and drain regions) are dependent upon the height of        the polysilicon, so it does not scale in proportion to the        lateral dimensions. Process steps which are becoming difficult        with scaling of vertical dimensions include formation of shallow        source and drain regions, their silicidation without causing        junction leakage, and etching and filling of contact holes to        the source and drain regions    -   6. It is well known to those skilled in the art to measure power        supply leakage current as an effective screen for detecting        defects introduced in the fabrication of the device. This method        is sometimes referred to as the I_(ddq) test by those skilled in        the art. This method is effective for CMOS with the minimum line        width above 350 nm. Scaling CMOS with the minimum line width        below 350 nm increases the inherent leakage current to levels        comparable to defect induced leakage current, rendering the        I_(ddq) test ineffective. Biasing the well voltage of the MOS        device to eliminate the inherent leakage current introduces new        elements of leakage such as gate leakage, junction tunneling        leakage, etc.

The prior art in junction field effect transistors dates back to the1950s when they were first reported. Since then, they have been coveredin numerous texts such as “Physics of Semiconductor Devices” by SimonSze and “Physics and Technology of Semiconductor Devices” by Andy Grove.Junction field effect devices were reported in both elemental andcompound semiconductors. Numerous circuits with junction field effecttransistors have been reported, as follows;

such as:

Nanver and Goudena, “Design considerations for Integrated High-Frequencyp-Channel JFET's ”, IEEE Transactions Electron Devices, vol. 35, No. 11,1988, pp. 1924-1933.

0. Ozawa, ” Electrical Properties of a Triode Like Silicon VerticalChannel JFET”, IEEE Transcations Electron Devices vol. ED-27, No. 11,1980, pp. 2115-2123.

H. Takanagi and G. Kano, “Complementary JFET Negative-ResistanceDevices”, IEEE Journal of Solid State Circuits, vol. SC-10, No. 6,December 1975, pp. 509-515.

A. Hamade and J. Albarran, “A JFET/Bipolar Eight-Channel AnalogMultiplexer”. IEEE Journal of Solid State Circuits, vol. SC-16, No. 6,December 1978.

K. Lehovec and R. Zuleeg, “Analysis of GaAs FET's for Integrated Logic”,IEEE Transaction on Electron Devices, vol. ED-27, No. 6, June 1980.

In addition, a report published by R. Zuleeg titled “Complementary GaAsLogic” dated 4 Aug., 1985 is cited as prior art. The authors have alsopublished the material in Electron Device Letters in 1984 in a papertitled “Double Implanted GaAs Complementary JFET's”.

A representative structure of a conventional n-channel JFET is shown inFIG. 8. The JFET is formed in an n-type substrate 810. It is containedin a p-well region marked 815. The body of the JFET is shown as 820,which is an n-type diffused region containing source (832), channel(838), and drain (834) regions. The gate region (836) is p-type, formedby diffusion into the substrate. Contacts to the source, drain, and gateregions are marked as 841, 842, and 840, respectively. The criticaldimension of the JFET is the gate length, marked as 855. It isdetermined by the minimum contact hole dimension 850, plus the necessaryoverlap required to ensure that the gate region encloses the gatecontact. The gate length 855 is significantly larger than 850. Thisfeature of construction of the prior art JFET limits the performance ofthese devices, since channel length is substantially larger than theminimum feature size. In addition, the capacitances of the verticalsidewalls of the gate diffusion to drain and source regions 861 and 862respectively are also quite large. The gate-drain sidewall capacitanceforms the Miller capacitance, a term known to those skilled in the art,and significantly limits the performance of the device at highfrequencies.

Accordingly, it is desirable to have an integrated circuit and devicestructure as well as a method for fabrication to address the abovementioned problems as the geometry continues to scale down. Optionally,it is also desirable to fabricate this new integrated circuit and devicestructure using a method similar to that for fabricating CMOS devices totake advantage of the existing facility and equipment infrastructure.

SUMMARY OF THE INVENTION

This invention describes a method of building complementary logiccircuits using Junction Field Effect Transistors (JFETs) in silicon.This invention is ideally suited for deep submicron dimensions,preferably below 65 nm.

In order to address the problems of the current CMOS and junction fieldeffect transistor technology as mentioned in the section above, thisinvention describes a system of semiconductor devices to remedy theseproblems, especially at minimum feature sizes of 65 nm and below. Thisinvention describes multiple methods and structures to build thesemiconductor devices and circuits which are similar to those used forCMOS devices. This feature of the invention allows it to be inserted inthe existing VLSI design and fabrication flow without any significantchange in the overall system for designing and fabricating VLSIcircuits. The main attributes of the invention are as follows;

-   -   1. It allows significant reduction in the power dissipation of        the circuit.    -   2. It allows significant reduction in the gate capacitance.    -   3. It allows significant reduction in the leakage current at the        gate.    -   4. It allows significant reduction in the leakage current        between source and drain.    -   5. It allows significant simplification of the VLSI        manufacturing process.    -   6. It leverages the design infrastructure developed for CMOS        technology. It is contemplated that all complex logic functions        available in prior art CMOS cell library can be implemented with        the device of the present invention. These complex logic        functions include but not limited to inverter, nand, nor, latch,        flip-flop, counter, multiplexer, encoder, decoder, multiplier,        arithmetic logic unit, programmable cell, memory cell,        micro-controller, JPEG decoder, and MPEG decoder.    -   7. It leverages the existing manufacturing and test        infrastructure used for CMOS.    -   8. It allows the method of measuring power supply leakage        current as an effective screen for detecting defects introduced        in the fabrication of the device.

The basis of this invention is a complementary Junction Field EffectTransistor (JFET) which is operated in the enhancement mode. As is knownto those skilled in the art, enhancement mode, it implies that thetransistor is in the “OFF” state when the potential between the gate andthe source terminals is zero. In this state, there is little or nocurrent flow between drain and source when a positive (negative) bias isapplied at the drain terminal of the n-channel (p-channel) JFET. As thepotential at the gate is increased (decreased), the n-channel(p-channel) JFET enters the high conduction regime. In this mode, afinite current flows between the drain and the source upon applicationof positive (negative) bias at the drain. The limitation of traditionalenhancement mode JFET devices is that their current drive is limited bythe maximum gate voltage, which is less than one diode drop. A gatevoltage in excess of one diode drop (the built-in potential) turns onthe gate-channel diode which is an undesirable mode of operation for theJFET. This limitation is resolved in the the present invention bylimiting the biasing voltage, VDD, to less than one diode drop. Theproblem of low current drive of the JFET is addressed by scaling thechannel length of the JFET to sub-100 nanometer dimensions. When theJFET gate length is less than 70 nanometers and the power supply voltageis 0.5 V, the current output of the complementary JFET devices and theswitching speed of the inverters made with the complementary JFETdevices compare favorably with conventional CMOS devices.

It should be noted that although the speed-power performance of theJFETs becomes comparable with the CMOS devices at sub-70 nanometerdimensions, the maximum power supply voltage for the JFETs is stilllimited to below a diode drop. To satisfy certain applications whichrequire an interface to an external circuit driven to higher voltagelevels, this invention includes the structures and methods to build CMOSdevices also. The CMOS devices described in this invention differ fromconventional CMOS along the following points;

-   -   1. CMOS is integrated with complementary JFETs.    -   2. In one embodiment of the invention, CMOS is built without any        “spacer”.    -   3. In the above embodiment of the invention, contacts to the        CMOS terminals are planar, or at the same level, which improves        the manufacturability of the devices.    -   4. Other salient features of this CMOS device have been        described above.

BRIEF DESCRIPTION OF DRAWINGS

So that the manner in which the above recited features, advantages andobjects of the present invention are attained and can be understood indetail, a more particular description of the invention, brieflysummarized above, may be had by reference to the embodiments thereofwhich are illustrated in the appended drawings.

It is to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the present invention may admit toother equally effective embodiments.

FIG. 1 is a diagram illustrating a complementary JFET inverter.

FIG. 2 a is a diagram of a complementary JFET inverter with the welltied to the source.

FIG. 2 b is a diagram of a complementary JFET inverter with the welltied to the gate.

FIG. 2 c is a diagram of a complementary JFET inverter with the welltied to an external pad.

FIG. 3 a is a diagram of the layout of a JFET.

FIG. 3 b is a diagram of the cross section of a poly gate JFETcorresponding to FIG. 3 a.

FIG. 3 c is a graph showing the doping profile of a JFET through thegate and the channel.

FIG. 4 is a cross section of a poly gate JFET similar to a conventionalMOSFET.

FIG. 5 is a cross section of a poly gate planar JFET with all thecontacts made through polysilicon.

FIG. 6 is a cross section of a poly gate planar JFET with the channelregion grown epitaxially.

FIG. 7 is a cross section of a poly gate planar JFET with the channelregion grown epitaxially and the polycrystalline semiconductor alloygate comprising carbon, silicon, and germanium.

FIG. 8 is a cross section of a conventional n-channel JFET.

FIG. 9 is a flow chart of building the complementary JFET structure asshown in FIG. 5. Each step of the flow chart is further illustrated inFIGS. 10-20.

FIG. 10 is the cross section of the silicon wafer after the formation ofthe isolation region.

FIG. 11 is the cross section of the silicon wafer after the formation ofthe n-well and the p-well.

FIG. 12 a is the cross section of the silicon wafer after the formationof the channel region of nJFET.

FIG. 12 b is the cross section of the silicon wafer after the formationof the channel region of the pJFET.

FIG. 13 is the cross section of the silicon wafer after polysilicondeposition and selective doping of polysilicon.

FIG. 14 is the cross section of the silicon wafer after deposition of aprotective coating on the polysilicon layer.

FIG. 15 is the cross section of the silicon wafer after polysilicondefinition by photolithography and etching.

FIG. 16 a is the cross section of the silicon wafer after doping thelink region between the gate and the drain/source of the p-channel JFET.

FIG. 16 b is the cross section of the silicon wafer after doping thelink region between the gate and the drain/source of the n-channel JFET.

FIG. 17 is the cross section of the silicon wafer after filling theempty space between the polysilicon structures and then performingplanarization.

FIG. 18 is the cross section of the silicon wafer after formation ofself aligned silicide on the exposed polysilicon surfaces.

FIG. 19 is the cross section of the silicon wafer after deposition ofthe dielectric layer on polysilicon and the subsequent etching ofcontact holes.

FIG. 20 is the cross section of the silicon wafer after metal depositionand definition.

FIGS. 21-24 describe the formation of a MOS transistor using the processadapted from FIG. 9.

FIG. 21 shows the cross section of the silicon wafer after formation ofisolation regions, well structures, threshold implants and gatedielectric. The gate dielectric is grown and etched from the waferexcept for regions surrounding the MOS gate region.

FIG. 22 shows the cross section of the silicon wafer after polysilicondeposition, polysilicon doping and formation of a protective layer ontop of the polysilicon.

FIG. 23 shows the cross section of the silicon wafer after polysilicondefinition.

FIG. 24 shows the cross section of the silicon wafer after the linkregion is formed between the gate and the source/drain by ionimplantation.

FIG. 25 shows the complete flow for forming JFETs and MOSFETs on thesame wafer. Each step is further illustrated in FIGS. 26-30.

FIG. 26 shows the cross section of the silicon wafer after the n-welland the p-well have been formed.

FIG. 27 shows the cross section of the silicon wafer after the channelfor the JFET is formed.

FIG. 28 shows the cross section of the silicon wafer after the channelfor MOS is formed.

FIG. 29 shows the cross section of the silicon wafer after source anddrain regions for MOS and JFET are formed.

FIG. 30 a shows the cross section of the silicon wafer after the contactholes and metal connections are formed.

FIG. 30 b shows The layout of the NMOS and nJFET after the contact holesand metal connections are formed.

DETAILED DESCRIPTION OF THE INVENTION

The circuit diagram of an inverter built with this invention is shown inFIG. 1. The operating terminal voltages of the two transistors under ONand OFF conditions are shown in Table 1: TABLE 1 Terminal Voltages atthe CFET Gate Under ON and OFF Conditions. Vin Vout FT1 FT2 0 Vdd ON OFFVdd 0 OFF ON

The operation of the circuit shown in FIG. 1 is remarkably similar tothe operation of the corresponding CMOS circuit. The JFETs operate atvoltage levels in this invention which are similar to the voltage levelsof the conventional CMOS technology. The input voltage varies between 0and Vdd. The output voltage varies between Vdd and 0 in an inverserelationship to the input voltage. Thus, for the two states of theinverter, when the applied voltage at the input terminal is 0 and Vdd,the output voltage is Vdd and zero respectively. This is achieved by thetwo transistors FT1 and FT2 being switched ON and OFF, as stated inTable 1 above.

As is-known to those skilled in the art, JFETs operate by applying acontrol signal at the gate, which controls the conductioncharacteristics of the channel between the source and the drain. Thegate forms a p-n junction with the channel. The voltage at the gate withrespect to the source controls the width of the depletion region of thegate-to-channel junction. The undepleted part of the channel isavailable for conduction. Thus, the channel is turned ON and OFF byapplying appropriate voltages at the gate and source terminals of theJFET transistor. Current will flow between the source and the drain whenthe channel is turned ON and the appropriate voltage is applied to thedrain.

The JFET transistors FT1 and FT2 in the JFET inverter function in amanner very similar to the MOS transistors in a CMOS inverter. Theoperation of a CMOS inverter is well known to those skilled in the art.The p-channel JFET (FT1) is connected to the power supply at its sourceterminal. The n-channel JFET (FT2) is connected to the ground at itssource terminal. The drain terminals of the two transistors areconnected together and to the output terminal of the gate. The gate ofthe p-channel JFET FT1 and the gate of n-channel JFET FT2 are connectedtogether and to the input terminal of the gate, as shown in FIG. 1. Thiscircuit configuration is called a CFET inverter in the remainder of thisdocument. In general, gates formed in a similar manner with p-channeland n-channel JFETs are called CFET gates.

The functioning of the inverter is explained in greater detail here inorder to reveal the full implementation of the invention. This isaccomplished by first explaining the voltages at the source and thedrain terminals of the transistor, which are shown in Table 2. In anexemplary and non-limiting illustration, the power supply voltage isfixed at 0.5V. TABLE 2 Junction voltages for JFETs in CFET Gate FT1 FT2Vin Vout VGS VDS VGS VDS 0.5 0 0 V −0.5 0.5 0 0 0.5 −0.5 0 0 0.5

The gate of the p-channel JFET is made of n-type silicon and the channelis doped p-type. The doping profile of the p-channel JFET is designed toturn off conduction through the channel when the voltage on the gateterminal is at zero volts relative to the source terminal. This deviceis an enhancement mode device. This attribute of the p-channel JFET isdue to the built-in potential at the p-n junction between the gate(p-type) and the channel (n-type). Since the source of the FT1 is tiedto VDD at 0.5V, the external bias between the n-type channel and p-typegate is 0.0V when the gate of the FT1 is also at 0.5 V. This representsthe FT1 in the OFF condition. As the bias at the gate of the p-channeltransistor is decreased to 0.0V, the negative voltage between the gateand the source terminals changes to −0.5V, which causes the depletionlayer to collapse and allows the flow of current from source to drain.This represents the FT1 in the ON condition.

An important teaching of this invention is how to limit gate currentwhen FT1 is in the ON condition. The channel-to-gate diode is forwardbiased at 0.5 V under this condition, so there is a finite leakagecurrent which flows through the gate of the transistor. It is termed thegate leakage. The magnitude of the gate leakage is controlled by thebuilt-in potential across the gate-channel junction. The built-inpotential limits the gate leakage current to a very small amount whenthis CFET inverter is operated with supply voltages (VDD) at or below0.5V for silicon-based circuits. Thus, the CFET inverter works in amanner similar to the CMOS inverter in both design and operatingcharacteristics. The limit for supply voltages may be different forother materials because of differences in the built-in potential.Similarly, the bias voltages for the n-channel JFET are reversed; thetransistor is turned “OFF” when the gate-source bias is reduced to zeroand it is turned on when the gate-source bias is equal to the supplyvoltage VDD, which is limited to 0.5V in order to restrict the gatecurrent. The gate current of a typical gate-channel junction isprojected in the range of 1 uA/cm² to 100 mA/cm². In contrast, for anMOS transistor made with 45 nanometer lithography and appropriatelyscaled gate dielectric thickness, the gate current is projected to be inexcess of 1000 A/cm².

The input capacitance of the JFET transistor is the junction capacitanceof the diode formed by the gate-channel terminals. The capacitance ofthis diode is in the range of 10⁻⁸ F/cm² to 10⁻⁶ F/cm², determined bythe thickness of the depletion layer width of the junction, which is inthe range of 100 angstroms to 3000 angstroms. The input capacitance ofan MOS transistor made with 45 nanometer design rules and 10 angstromthick oxide is an order of magnitude higher than the corresponding inputcapacitance of the JFET. This feature makes the JFET extremelyattractive from the perspective of low power operation.

The JFET transistors also have a fourth electrical terminal, namely thewell. One embodiment of the invention is described here with the wellconnected to the source terminal for both the JFETs, as shown in FIG. 2a.

FIG. 2 b shows an alternate embodiment of the invention, in which thewell is tied to the gate and used for modulating the conductivity of thechannel from both the top and the bottom.

FIG. 2 c shows yet another embodiment of the invention, in which thewell of the n-channel JFET is connected to an external terminal, whichcan be used for applying any signal to the JFET. In yet anotherembodiment of the invention, the well of the n-channel JFET is leftfloating. The corresponding description also applies to the p-channelJFET. It is well known to those skilled in the art to measure powersupply leakage current as an effective screen for detecting defectsintroduced in the fabrication of the device. This method is sometimesreferred to as the I_(ddq) test by those skilled in the art. This methodis effective for CMOS with the minimum line width above 350 nm. ScalingCMOS with the minimum line width below 350 nm increases the inherentleakage current to be comparable to the defect induced leakage current,thus rendering the I_(ddq) test ineffective. For MOS devices with theminimum line width below 100 nm, biasing the well voltage of the MOSdevice to eliminate the inherent leakage current introduces new elementsof leakage such as gate leakage, junction tunneling leakage, etc. In thepresent invention, biasing the well voltage of the JFET can effectivelyreduce the inherent leakage current to the pico-ampere range. This makesthe I_(ddq) test an effective screen for detecting defects introduced inthe fabrication of devices with the minimum line width below 100 nm.

FIG. 3 a shows an exemplary and non-limiting layout of the JFETtransistor which is used to build this circuit structure. The source,drain, gate and well tap of the n-channel JFET are given by 330, 340,375, and 368 respectively. The contacts to these terminals are marked by372, 374, 373, and 371 respectively.

FIG. 3 b shows a cross-section of the structure of an n-channel JFETwhich consists of four terminals; source (330), gate (370), drain (340),and p-well (310). The JFET is formed in a region of silicon marked as315. The JFET is isolated from the surrounding semiconductor by regionsmarked as 320; these are filled with an insulating material such assilicon dioxide. The channel between the source and drain is shown asobject 350. For the n-channel JFET, the source and drain are highlydoped n-type regions formed by doping silicon with donor type impuritiessuch as phosphorous, arsenic or antimony. The well is doped by acceptorimpurities such as boron or indium. The channel is a narrow region whichis doped n-type connecting source and drain. The gate is a shallowp-type region 370 formed within the channel by methods such as diffusionof dopants from the heavily p+ doped polysilicon region 375.

A doping profile of the transistor at varying depths from the siliconsurface through the gate (370) and channel (350) is shown in FIG. 3 c.The curve 381 is an exemplary doping profile of the gate region startingfrom the silicon surface. Curves 382, 383, and 384 represent the dopingprofile of the channel, well, and the bulk regions. For the n-JFET, 381is the doping profile of the p-type gate region, 382 is the profile ofthe n-type channel region, 383 is the profile of the p-type well region,and 384 is the profile of the surrounding n-type bulk region. Thegate-channel junction is given by 385, the channel-well junction isgiven by 386, and the well-bulk region junction is given by 387. Thedepth of the junction between gate and channel from the surface ofsilicon (385) is less than the depth of the junction between the channeland the p-well (386).

This invention also teaches other methods for forming the p-type gatejunction, such as ion-implantation. This invention also covers othermethods to dope the gate, such as plasma immersion implant, as is wellknown to those skilled in the art.

In FIG. 3 b, the Region 375 is a slab of polysilicon which is dopedheavily p-type and acts as the source for doping of the gate 370. Thep-type gate is used to control the conduction across the channel fromsource to drain. By this novel construction technique, the gate isdiffused in the channel region from heavily doped polysilicon which alsoforms an ohmic contact with the gate. This allows the polysilicon to beused to connect the gate to the external circuit.

The ohmic contact to the well is made by the well tap marked as object368. The contacts to the four terminals of the JFET, namely well,source, gate, and drain are shown in FIG. 3 b also, as objects 371, 372,373, and 374, respectively. The region underneath the p-well tap 368 isdoped heavily with p-type impurities to make good ohmic contact. Thep-well 310 is formed in an n-well marked as 315 for applications wherethe p-well of the JFET has to be isolated. For applications where thep-well is connected to the ground potential, the need for the n-well isobviated. This invention covers both of these cases.

The doping types are reversed for the p-channel JFET in relation tothose described in FIG. 3 b and 3 c, i.e. the p-type regions arereplaced by n-type regions and vice versa. It should be pointed out thatthe novelty of the invention of doping the gate of the JFET withpolycrystalline silicon 375 is maintained for the p-channel JFET also.

An alternate embodiment of the JFET is shown in FIG. 4. This figureshows the cross section of an n-channel JFET, which is very similar toan MOS transistor. The structure of the n-channel JFET is describedhere. It is implied that this structure will also be replicated for thep-channel JFET with appropriate changes in doping, as described in theparagraph above. The JFET is shown as object 400. The p-well in whichthe JFET is formed is marked as object 310. The isolation for the JFETis provided by a region filled with an insulating material such assilicon dioxide or other suitable materials in object 320. Thisstructure is similar to the corresponding structure shown in FIG. 3. Theheavily doped n-type regions form the source and drain region and aremarked 420 and 430, respectively. The channel region between source anddrain is lightly doped n-type and is marked 450. The gate region isdoped p-type and is marked 440. This region is diffused from thepolysilicon with heavy p-type doping marked as 460. An insulating regionmarked 465 is inserted here, surrounding the gate, consisting of acombination of silicon dioxide and nitride layers. This object is calleda “spacer” in this document. In an embodiment of the invention, topsurfaces of the regions 420, 430, 460 and 368 are covered with a highlyconducting layer of one of the metallic compounds called silicides,marked as 462. The silicide layer is self aligned to the well tap,source, drain, and gate regions, implying that the silicide is formedonly in the regions where there is exposed silicon or polysilicon. Themajor purpose served by the spacer is that it isolates the source anddrain regions from the gate region when self aligned silicides areformed. It also allows efficient distribution of current from thecontact inside the device. The contacts to the well tap, source, drain,and gate regions are done in a manner similar to that in FIG. 3, and aremarked as 371, 372, 373, and 374, respectively.

In an alternate embodiment of the JFET, as shown in FIG. 5, contacts toall the terminals of the JFET, namely source, gate, drain, and well, areall made with polysilicon. This structure has the desirable attribute ofhaving contacts to all terminals at the same level. The n-channel JFETis made in a p-well marked 310, which is isolated from all sides by aninsulated region 320. This structure is similar to the correspondingstructure shown in FIG. 3. The source of the JFET is formed by acombination of heavily n-doped regions 520 and 522. The drain of theJFET is also formed by a combination of heavily doped n-type regions 524and 526. The channel 550 is a shallow n-type doped region between drainand source. The p-type gate region diffused in silicon is marked as 540.Blocks 530 and 532 are heavily n-type polysilicon doped regions. Theregion 520 is formed by diffusing n-type impurities from the polysiliconinto the silicon. Similarly, region 524 is formed by diffusion of n-typeimpurities from the polysilicon region 532 into the silicon. The gateregion 540 is formed by diffusion of the p-type impurities from thep-type polysilicon 560 into the silicon. The regions 522 and 526 connectthe source and the drain regions 520 and 524, respectively, to thechannel 550. The polysilicon regions marked as 530, 532 and 560 are inohmic contact with regions 520, 524, and 540 respectively. The regions522 and 526 are formed by external doping such as ion implantation,plasma immersion implantation, or other similar doping methods. The welltap is formed by ohmic contact between the heavily p-doped polysilicon562 and the p-type region 368. The contacts to the transistor are madeat the top of the objects 530, 532 and 560 and 562. In order to reduceohmic contact resistance of these regions, self aligned silicide isformed on top of the polysilicon layer, marked as 580. In an alternateembodiment of this invention, contacts to the terminals of thetransistor are made directly to the polysilicon.

In an alternate embodiment of this invention, the top surface of thesilicon substrate is formed by epitaxial deposition of silicon-germaniumalloy, which is doped appropriately to form the channel and the gate,shown in FIG. 6. The structure is built-in a well 310 with isolationregions 320. The major feature of this embodiment is that the channel ofthe JFET is formed on an epitaxially deposited layer ofsilicon-germanium alloy marked as object 670. The mobility of thesilicon-germanium alloy is much higher than silicon, which increases theperformance of the JFET, especially at high frequencies. This epitaxiallayer is deposited on the transistor after the formation of theisolation structure on the wafer. The epitaxial layer is depositedselectively in this embodiment only on the islands where the channel isto be formed. The epitaxial layer for the channel of the nJFET isdeposited in one step, and the epitaxial layer for the channel of thepJFET is deposited in the next step. In another embodiment, theepitaxial layer is deposited on the wafer prior to the formation of theisolation structure. In yet another embodiment of this invention, thechannel region is formed by a strained silicon-germanium alloy. Anotherembodiment of the invention teaches the use of silicon-germanium-carbonto build the channel region of the JFETs. The terms silicon-germaniumalloy and strained alloys are well known to those skilled in the art.The silicon-germanium alloy is formed by deposition of a mixture ofsilicon and germanium atoms epitaxially on the silicon substrate. Theremaining structure of the JFET is similar to the structure shown inFIG. 5. The doping of the epitaxially deposited channel is controlled byexternal doping, such as ion implantation. Alternately, the epitaxiallydeposited material is doped during deposition by methods such as atomiclayer epitaxy and similar techniques. The epitaxial deposition steps arealso applicable to the JFET structures shown in FIGS. 3 and 4.

Another embodiment of this invention, shown in FIG. 7, involves the useof a high band gap material such as silicon carbide or silicon-germaniumcarbide to form the gate contact region 744. This feature is implementedin this invention in order to increase the barrier height at the p-njunction formed at the gate 640-channel 650 junction. The high band gapmaterial of the gate contact region 744 in proximity to the gate region640 effectively increases the barrier height at the p-n junction formedat the gate 640-channel 650 junction. The higher gate-channel junctionbuilt-in potential reduces the saturation current across the junction,and allows an increase in the maximum voltage which can be applied tothe gate-channel diode to forward bias it without causing a significantamount of gate current to flow across the diode. Since the maximumvoltage at the gate is equal to the power supply voltage of theinverter, a higher power supply voltage becomes possible, increasing thedrive strength of the transistors and resulting in faster switching ofthe inverter. As shown in FIG. 7 for this embodiment, thepolycrystalline silicon carbide material is used in place of polysiliconto form the electrodes. The use of a high band gap material such aspolycrystalline silicon carbide reduces the leakage current of the gatejunction when the gate-channel diode is weakly forward biased during theON state of the transistor. This invention teaches the use of variousphases of silicon carbide for this purpose, namely 3C, 4H, and 6H.Further, this invention teaches the use of various other electrodematerials which can be used to form a rectifying junction with thesilicon substrate, including ternary alloys of silicon-germanium-carbonand various other compound semiconductors such asgallium-aluminum-arsenide-phosphide. In an alternate embodiment of theinvention, use of materials for the gate such as silicon carbide is madealong with epitaxially deposited high mobility materials such assilicon-germanium at the same time. The composition of the gate materialis varied during deposition. The electrode extensions for source, drain,gate, and well tap, marked as 730, 732, 744, and 752, are made of highband gap semiconductor material such as silicon carbide. A self alignedconducting layer is formed on the top of these electrodes and is markedas 750. The polycrystalline semiconducting materials are dopedappropriately, as described in the previous paragraphs. The othercomponents of the transistors remain similar to the nJFET structuredescribed in FIG. 6.

An exemplary embodiment of the invention teaches the use of asilicon-carbide layer near the surface of the silicon to a depth rangingfrom 10 Å to 1000 Å, followed by deposition of polysilicon to a depth of10 Å to 2500 Å. The composition of the polycrystalline layer is variedto facilitate accurate monitoring of the etching process, in which thepolycrystalline material is etched fast until the composition markingthe bottom of the layer is detected and then slowly with a selectiveetching process until all the polycrystalline material is etched.Detailed explanation of the fabrication process using polycrystallinesilicon carbide is explained later in this document.

Next, an exemplary but non-limiting method of building the complementaryJFET structure as shown in FIG. 5 is illustrated as the flow chart inFIG. 9. Each step in the flow chart is further illustrated in FIGS.10-20. Step 905 is illustrated in FIG. 10. Step 910 is illustrated inFIG. 11. Step 915 is illustrated in FIG. 12. Step 920 and 925 areillustrated in FIG. 13. Step 930 is illustrated in FIG. 14. Step 935 isillustrated in FIG. 15. Step 940 is illustrated in FIG. 16. Step 950 isillustrated in FIG. 17. Step 955 is illustrated in FIG. 18. Step 960 isillustrated in FIG. 19. Step 965 is illustrated in FIG. 20.

FIG. 10 shows the cross sectional view of a semiconductor substrateafter the preliminary steps during the fabrication have been completedto achieve the isolation of the various regions where active deviceswill be formed by a combination of etching, thermal oxidation anddeposition of silicon dioxide. Regions 1001-1005 represent the regionswhich are filled with insulating material consisting of silicon oxideand nitride by a combination of etching, deposition and thermal growth.The details of the process for the formation of these regions are wellknown to those skilled in the art and are beyond the scope of thisdisclosure. Regions 1011-1014 represent regions where active transistorsare formed in the subsequent steps.

FIG. 11 shows the formation of n-wells and p-wells by doping the activeregions with appropriate impurities in regions 1101 and 1102. For then-wells in region 1102, phosphorous or arsenic atoms are implanted. Thedoping level of the implant varies between 1.0×10¹¹ /cm² to 1.0×10¹⁴/cm². The energy of implantation varies between 10 KeV and 400 KeV. Forthe p-wells in region 1101, boron is introduced by ion implantation witha dose varying between 1.0×10¹¹ /cm² and 1.0×10¹⁴ /cm² and with theenergy of implantation varying between 10 KeV and 400 KeV. Multipleimplants may be used to achieve the desired impurity doping profile. Inorder to selectively implant regions with n-type and p-type impurities,implants are done using photoresist masks to shield the region notdesigned to receive the implant. Additional implants of boron are doneunder the isolation regions 1001-1005 to increase the doping in theregion underneath the oxide and prevent any leakage between the twoadjoining n-wells. The wafers are heat-treated to achieve the desiredimpurity doping profile.

FIGS. 12 a and 12 b show the formation of channel regions 1202 for thenJFET and 1222 for the pJFET respectively. The channel region is formedby selective implantation using photoresist masks. For the nJFET, thechannel is formed by ion implantation with an n-type dopant such asarsenic, phosphorous, or antimony with an implant dose of 2.0×10¹¹ /cm²to 1.0×10¹⁴ /cm² and with the implant energy between 1 and 100 KeV,shown as region 1202 in FIG. 12 a. Also shown in the figure is thephotoresist 1210 covering the regions where the n-channel implant is tobe blocked. Region 1222 in FIG. 12 b is implanted with p-type impuritiessuch as boron, indium or thallium to form the channel of the pJFET. Inan alternate embodiment of the invention, the channel region is formedby plasma immersion doping. Alternately, the channel is formed byepitaxial growth of the channel region consisting of silicon,silicon-germanium binary alloys, or silicon-germanium-carbon tertiaryalloys. This invention teaches the variations in formation of epitaxialregions by selective epitaxial growth of channel regions for n-channeland p-channel, as well as a single deposition of the channel regions forboth nJFET and pJFET, followed by selective doping. Yet anotherembodiment of the invention covers the instance in which the channelregions are doped during deposition by methods such as atomic layerepitaxy.

Next, a layer of polysilicon is deposited over the whole wafer, as shownin FIG. 13. The thickness of polysilicon deposited on the wafer variesbetween 100 Å and 10,000 Å. The polysilicon is selectively doped to formregions which will eventually become the source, drain, gate, and wellcontacts of the JFETs using photoresist as masks. The details of thephotolithographic process are omitted here for the sake of brevity. Asshown in 1300, the region marked as 1310 is doped with a heavy boronimplant to a dose ranging between 1×10¹³ /cm² and 1×10¹⁶ /cm². It isdesigned to act as the contact for the well region of the n-JFET. Region1314 is designed to act as the gate contact for the n-JFET. It is dopedheavily p-type with the parameters similar to those of region 1310.Regions 1312 and 1316 are doped heavily with n-type dopants(phosphorous, arsenic, and antimony) to a dose ranging between 1×10¹³/cm² and 1×10¹⁶ /cm².

The p-JFET is formed with regions 1320 and 1324 acting as the source anddrain contacts (p type), respectively, region 1322 as the gate (n type),and region 1326 as the contact to the well tap (n type). Regions 1320and 1324 are doped with a heavy concentration of boron atoms to a doseranging between 1×10¹³ /cm² and 1×10¹⁶ /cm² and are designed to act asthe source and drain contacts of the pJFET respectively. Similarly,regions 1322 and 1326 are doped heavily n-type and are designed to actas gate and well contacts of pJFET. In an alternate embodiment, a layerof oxide is deposited on top of the polysilicon layer before doing theion implantation. The thickness of this layer varies between 20 Å and500 Å. In another embodiment, layers of oxide and nitride are depositedon top of the polysilicon prior to ion implantation, with the thicknessof the oxide and nitride films varying between 10 Å and 500 Å.

FIG. 14 shows the cross section of the silicon wafer with thepolysilicon layer doped with impurities, and a protective layer 1410 ontop of the polysilicon layer. The polysilicon layer with impuritiesimplanted in various regions is used as a source of indirect diffusionof those impurities into the silicon to form the source, drain, and gatejunctions and ohmic connections to the well. Regions 1422 and 1426 arethe source and drain regions of the nJFET which are diffused frompolysilicon regions 1312 and 1316. Region 1424 is the n-type channel.The gate region, marked as 1428, is diffused into the silicon from thep-doped polysilicon. Region 1420 is the p-type region (well tap) formedin the silicon by diffusion from the polysilicon region 1310 and formsan ohmic contact to the p-well which contains the nJFET. Similarly, thepJFET contacts in the silicon are formed by regions 1430 as the source,1432 as the channel, region 1434 as the drain, region 1436 as the wellcontact, and region 1438 as the gate region of the pJFET. In analternate embodiment, multiple ion implants, varying the implant doseand energy,; of n-type and p-type dopants in polysilicon are made toform the well contacts, source, drain, and gate regions.

After diffusion of the various regions of the JFETs into the silicon,the gate patterning process takes place. Using an optical lithographicprocess, a layer of an anti-reflective coating, followed by a layer ofphotoresist are coated on the wafer. The thickness of these layersdepends upon the selection of the photoresist, as is known to thoseskilled in the art. The photoresist layer is exposed and variousterminals are delineated in the photoresist, marked as 1510 in FIG. 15.Alternate embodiment of this invention includes other methods ofpatterning the photoresist, including imprint lithography and e-beamlithography. With the photoresist layer as the mask, the protectivelayer above the polysilicon is etched first. Next, the polysilicon layeris etched, with the grooves such as 1512 reaching the bottom of thepolysilicon layer. This step isolates the various terminalselectrically, as shown in 1500. For patterning the photoresist, variousprocesses such as optical lithography, immersion lithography, imprintlithography, direct write e-beam lithography, x-ray lithography, orextreme ultraviolet lithography are used.

FIG. 16 a is the cross section of the silicon wafer after doping thelink region between the gate and the drain/source of the p-channel JFET.After etching the polysilicon layer, the region between the heavilydoped regions and the channel are doped to form a low conductivity pathbetween the source and channel, and the drain and channel. It is calledthe link region (1620, 1622, 1652 and 1654) here. FIG. 16 a shows theformation of the link region for a pJFET. The section of the wafercontaining the nJFET is covered by photoresist 1610 during this stepwhile a suitable doping process such as ion implantation or plasmaimmersion implantation is used to dope the link regions of pJFET 1620and 1622. The link regions are formed to a junction depth independentfrom that of the neighboring source and drain regions, and are designedto provide a very low resistivity connection between source/drain andthe channel.

FIG. 16 b is the cross section of the silicon wafer after doping thelink region between the gate and the drain/source of the n-channel JFET.Object 1650 is the photoresist covering the regions where the implant isblocked, which contain the pJFET. Regions 1652 and 1654 in the siliconare the link regions formed by the implantation of n-type dopants. Afterion implantation, the dopants are activated by a rapid thermal annealingprocess. An oxidation step, at temperatures ranging between 700 C and950 C and for times ranging between 10 seconds and 20 minutes, is alsoperformed to oxidize the region of silicon damaged during etching.

FIG. 17 shows the cross section of the wafer after the gap between thepolysilicon blocks is filled with an insulating material such as silicondioxide and then processed, using a method such aschemical-mechanical-polishing, to provide a nearly planar surface at thesame level as the polysilicon layer. The technique of filling insulatingmaterial in between the polysilicon blocks by depositing silicon dioxideusing chemical vapor deposition or plasma assisted chemical vapordeposition is one which is widely used in semiconductor manufacturing.One such process employs the deposition of oxide by a low temperatureplasma-activated reaction between silane and oxygen in gaseous form. Theprotective layer 1410 is finally removed to expose the bare polysiliconsurface.

FIG. 18 is the cross section of the silicon wafer after formation ofself aligned silicide on the exposed polysilicon surfaces. A layer of ametal such as nickel, cobalt, titanium, platinum, palladium, or otherrefractory metal is deposited on the polysilicon surface and annealedsuch that the exposed regions of polysilicon form a binary compound withthe metal layer known as “metal silicides”. The metal silicide is a veryhighly conductive substance. The preferred thickness of the depositedmetal is between 50 Å and 1000 Å on an atomically clean surface ofpolysilicon. The wafers are heated in a rapid anneal furnace attemperatures between 200 C and 800 C for a time period between 10seconds and 30 minutes to form silicides selectively where metal is incontact with a silicon or polysilicon layer. After the reaction betweenthe metal layer and silicon has taken place, the excess metal is removedfrom the wafer by a chemical etching process which does not affect thesilicide layer. Unreacted metal is selectively etched off usingappropriate solvents, leaving only metal silicide over the exposedsilicon and polysilicon regions 1801. For titanium and cobalt, a mixtureof hydrogen peroxide and ammonium hydroxide is used in ratio of 1:0.1 to1:10 as appropriate at room temperature, although temperatures aboveroom temperatures can also be used. Thus, a self aligned layer ofsilicide is formed on polysilicon. FIG. 18 shows the cross section ofthe device after formation of silicide on the polysilicon source, drain,gate, and well tap terminals. This polysilicon layer is also used as alocal interconnect, whereby regions of silicided n-type polysilicon andp-type polysilicon are used for making ohmic contacts.

The next process step consists of depositing a dielectric (oxide) layer,etching contact holes in the oxide layer, and forming contact holes forthe source, drain, gate and well tap terminals, and continuing with theconventional metal interconnect formation process as practiced in theformation of semiconductor chips. A cross section of the wafer afterdielectric deposition and contact hole etch is shown in FIG. 19. Themetal deposition and etch is shown in FIG. 20.

This process can be adapted for making MOS transistors along with JFETs.One application of this adaptation is to include CMOS-compatible I/Os onthe chip. The process to make MOS transistors is described next. FIG. 21shows the cross section of a wafer after the formation of the n-wellsand p-wells for JFETs and MOSFETs. The threshold (V_(t)) adjust implantsfor the MOSFETs are also completed. In addition, the formation ofchannel regions for the JFETs is also completed. A layer of gatedielectric (oxide or nitrogenated oxide) is grown on the wafer. Thislayer of oxide is etched away from the wafer except in the regionssurrounding the gate of the MOSFETs. This oxide layer is shown as object2110. In an alternate embodiment of this invention, a thin layer ofamorphous silicon is deposited on top of the gate dielectric immediatelyafter the oxide is grown. The thickness of this amorphous layer issufficient to prevent damage to the underlying gate dielectric duringthe next photomasking and etching step. The preferred thickness of thisamorphous silicon layer is between 10 Å and 5000 Å. In an alternateembodiment of the invention, the oxide layer is formed first, and thechannel for the JFETs is formed afterwards.

Next, a layer of polysilicon is deposited on the wafer as shown in FIG.22. The polysilicon layer is covered by a protective layer of oxidemarked as 2220. With photolithography to define certain regions on thewafer, a layer of photoresist is selectively removed from the wafer andthe exposed areas are implanted with n-type and p-type dopants. Thisfigure shows the polysilicon layer with selectively doped regions.Region 2210 is doped p-type, region 2212 is doped n-type, region 2214 isdoped p-type, and region 2216 is doped n-type. The parameters for dopingthese regions are the same as the parameters described in FIG. 13.

The next step is the definition of the gate and the remaining electrodeson polysilicon, as shown in FIG. 23. It is accomplished by firstdefining the pattern in a photoresist layer 2330. Next, using thephotoresist layer as a mask, the polysilicon layer is etched to definethe electrodes. Region 2310 forms the well tap of the NMOS, region 2312forms the source of the NMOS, region 2314 forms the gate of the NMOS,region 2316 forms the drain of the NMOS, region 2320 forms the source ofthe PMOS, region 2322 forms the gate of the P-MOS, region 2324 forms thedrain region of the drain of the PMOS, and region 2326 forms the welltap for the PMOS. After etching the polysilicon layer, a short oxidationcycle is executed to form an oxide on the surface of silicon with athickness between 20 Å and 500 Å. Additional heat cycles are executed todiffuse the dopants into the silicon from the polysilicon in the drain,source, and the well tap regions while controlling the diffusion of thedopants from the polysilicon into the gate dielectric and into thechannel region.

FIG. 24 shows the formation of the link between the source, drain, andchannel regions by ion implantation. For NMOS, the links between thesource and the channel and the drain and the channel are formed by ionimplantation of n-type dopants marked as 2410 and 2412 respectively. ForPMOS, the links between the source and the channel and the drain and thechannel are formed by ion implantation of p-type dopants marked as 2420and 2422 respectively. A rapid thermal anneal is carried out to activatethe implant. The cross section of the wafer is very similar to the oneshown in FIG. 17. The wafer is processed by the method described inFIGS. 17 through 20.

The complete flow for forming JFETs and MOSFETs on the same wafer isshown in FIG. 25. The MOS transistors fabricated in this manner havemultiple advantages over the conventional method of building MOStransistors, as described here:

Conventional MOS transistors have a spacer which is used to separate thehighly doped source/drain regions from the gate. The dimensions of thespacer are dependent upon the vertical polysilicon dimension and otherprocessing parameters, and are not laterally scalable. The currentembodiment of the MOS transistor uses lithography to separate thesource/drain and the gate region, making this structure laterallyscalable.

Conventional MOS transistors have a lightly doped source and drainregion under the spacer, which limits the injection efficiency of thesource, or the maximum current which can be controlled by thetransistor. The current embodiment of the MOS transistor uses the linkregion as the source and drain junctions and it allows the doping ofthis region to be controlled independently.

Conventional MOS transistors have symmetrical source and drain regions.This embodiment allows asymmetrical source and drain junctions to beformed by spacing the source and drain polysilicon contacts from thegate asymmetrically.

Conventional MOS transistors have varying contact depths to thesource/drain and the gate terminals; the contacts to the source/drainterminals are made directly to silicon while the contact to the gateterminal is made to polysilicon which is elevated from the source/drainjunctions. This embodiment of MOS transistors etches all the contactholes to the polysilicon, keeping the depth of all the holes the same.

The conventional MOS transistors have to compromise the short channelperformance due to limitations imposed by a shallow source/drainjunction and the silicide formation on top of these junctions. Thisembodiment of the MOS transistors removes this limitation by placing thesilicide on top of the polysilicon for all the junctions. Also, theshallow source/drain junction in the silicon is formed by diffusion ofdopants from the polysilicon, which is a slower and more controllableprocess.

This method to build JFETs and MOSFETs allows a planar surface to existprior to contact hole etch. It also insures that the amount ofpolysilicon removed is limited, which is important in achieving auniform plasma etch. It is well known that the variation in the densityof the polysilicon pattern on the silicon wafer is responsible forvariation in the etch rate of polysilicon. In this method, this problemis overcome by the fact that the pattern density of polysilicon is muchhigher than in conventional process technology. Also, the contacts tothe various junctions are separated by the polysilicon layer, whichmakes it extremely convenient to form shallow source and drainjunctions.

Steps in FIG. 25 are further illustrated in FIG. 26-30.

FIG. 26 shows the cross section of a silicon wafer after the formationof isolation areas (2610), a p-well for forming NMOS transistors markedas 2601 and another p-well for forming nJFETs marked as 2602.Corresponding well structures to form PMOS transistors and pJFETs arealso formed but are omitted here for the sake of brevity. After theV_(t) adjust implants are performed in silicon for the MOS transistors,gate oxidation is performed over the whole wafer and a gate dielectriclayer of appropriate thickness is grown on the wafer, ranging between 10Å and 100 Å. It is shown as layer 2620 in this figure. In alternateembodiments of the invention, the gate dielectric is formed with a highdielectric coefficient material such as hafnium silicate and similarmaterials known to those skilled in the art.

FIG. 27 shows the wafer cross section after the following steps havebeen executed. First, the gate dielectric is removed by wet etching or asuitable technique such as plasma etching selectively from the regionswhere the JFET channel is to be formed. Next, the JFET channel is formedby ion implantation, marked as object 2710. After the formation of thechannel, a layer of polycrystalline material is deposited on the wafer.It is marked as 2720.

The gate electrodes of the JFET and the MOS transistors are implantedwith appropriate dopants. The gate regions of the NMOS transistor andthe pJFET are doped heavily n-type with arsenic, phosphorus, orantimony. The gate electrode regions of the PMOS and the nJFET areimplanted with p-type dopants, namely boron. The gate electrode regionsare implanted with a heavy dose of the dopants in the range of 1×10¹⁴/cm² to 1×10¹⁶ /cm². An alternate embodiment of the invention includesmultiple implant steps for forming the gate electrode region of the MOSand JFET transistors. The wafer is heated to distribute the dopantsthroughout the polysilicon layer.

A photomask is put on the wafer and the layer of polysilicon is etchedto define the gate electrodes for the transistors, as is shown in FIG.28. Object 2810 forms the gate of the NMOS transistor while the object2820 forms the gate electrode of the nJFET transistor. The gate of theNMOS transistor is formed with n-type polysilicon while the gate of thenJFET is formed with p-type polysilicon. After defining the gate, ashort oxidation cycle is executed to remove the damage from the surfaceof polysilicon. Layers of oxide and nitride are deposited next andetched anisotropically to form spacers adjacent to the gate electrodes.At the end of the spacer formation, the cross section of the wafer showsa gate electrode surrounded by spacers on both sides. The objects marked2830 are the spacers surrounding the gate. It should be noted here thatthe polysilicon on the nJFET islands (object 2602) does not have a layerof oxide underneath to stop the etch. So, the polysilicon etchingprocess has to be conducted very carefully so as not to over-etch thepolysilicon and etch into the silicon. Process steps to preventover-etching the polysilicon have been described earlier in thisapplication.

FIG. 29 shows the cross section of the silicon wafer after the sourceand drain regions for the MOS and JFET transistors are formed. Theprocess step consists of forming the Lightly Doped Drain (LDD) regionfor the NMOS transistors. This is done by selective ion implantation ofn-type dopants in the NMOS region 2601. This step is also accompaniedwith an implant of dopant of opposite polarity (p-type) to prevent thedepletion regions of drain and source from touching each other, causinga phenomenon known as “punch through”. This step is known as the“anti-punch-through” implant. The LDD and the anti-punch-throughimplants are performed at angle of incidence on the wafer ranging fromperfectly vertical to a tilt of 60% from the vertical. These regions aremarked as 2910 in the FIG. 29. A similar process is performed to createa low resistance region (link) between the channel of the JFET and thesource and drain regions. The links are formed adjacent to the gate ofthe JFET, marked as objects 2920. The source and drain regions areformed by ion implantation of n-type impurities for both NMOS and nJFETtransistors. The n-type ion implantation to form source and drainterminals for NMOS is a well established process. For the nJFET, thedoping type of source and drain is opposite to that of the gate. Theimplant parameters of the source and drain are adjusted to insure thatthe n-type dopants used for forming these terminals do not invert thepolarity of the gate region. The gate doping for the JFET is maintainedat a high level by implanting with n or p type dopants to a dose of1×10¹⁴ /cm² to 1×10¹⁶ /cm². The energy of the implantation is selectedbased on the polysilicon thickness. The doping of the source and drainof the JFET is kept lower than the gate doping in order to insure thatinversion of the gate doping does not occur. The source and drainregions of the NMOS transistor are marked as 2950 and 2952, and thesource and drain of the nJFET are marked as 2954 and 2956, respectively.

FIG. 30 a shows the cross section of the silicon wafer after contactholes and metal connections are formed. Following the source and drainformation, the self aligned silicide formation takes place by depositinga layer of metal such as cobalt, nickel, titanium, platinum, etc. andheating the wafer to allow the metal to react with the exposed siliconsurface, forming the silicide compound. The unused metal is washed awayby a wet chemical etch. This is followed by deposition of a layer ofoxide at temperatures below 600 C as a dielectric layer to cover thewhole wafer, as shown in FIG. 30 a. Contact holes 3010 are etched in thedielectric layer. Metallic alloys in single or multiple layers aredeposited over the wafer and they are patterned by a photolithographicprocess, followed by etching of the metal layer to form interconnectsfrom the transistors shown as object 3020. The layout of the NMOS andnJFET is shown in FIG. 30 b. The source, drain, and gate regions of theNMOS transistor are marked as 3050 and 3051, and 3054. Their respectivecontact holes are marked as 3060, 3061 and 3064. Similarly, source,drain, and gate regions of the nJFET are marked as objects 3052, 3053,and 3055, and their contact holes are marked as 3062, 3063, and 3065,respectively.

1. A junction field effect transistor comprising: a semiconductorsubstrate; a well region of a first conductivity type formed in thesemiconductor substrate and adjacent to a surface of the semiconductorsubstrate; an insulating region formed of dielectric material in thesemiconductor substrate and adjacent to the surface of the semiconductorsubstrate; wherein the insulating region surrounds the well region;first and second non-overlapping regions of the second conductivity typeopposite to the first conductivity type, formed in the well region andadjacent to the surface of the semiconductor substrate; wherein thefirst and the second regions respectively form the source and drainregions of the junction field effect transistor; a gate electrode regionof the first conductivity type comprising a first portion overlaying thesemiconductor substrate between the source and drain regions; a secondportion overlaying parts of the source and drain regions; and a thirdportion overlaying of the insulating region; a gate region of the firstconductivity type, formed in the well region immediately underneath theentire first portion of the gate electrode, wherein the gate region hasan impurity concentration doped from the gate electrode region; and achannel region of the second conductivity type, formed in the wellregion immediately underneath the entire gate region.
 2. The junctionfield effect transistor as in claim 1 wherein the semiconductorsubstrate comprises a material selected from a group consisting ofsilicon, germanium, silicon carbide, and silicon-germanium-carbon alloy.3. The junction field effect transistor as in claim 2 wherein thechannel region and the gate region are formed of epitaxially depositedsilicon-germanium-carbon alloy material on the semiconductor substrate.4. The junction field effect transistor as in claim 1 wherein the gateelectrode region comprises polycrystalline silicon.
 5. The junctionfield effect transistor as in claim 1 wherein the gate electrode regioncomprises silicon-germanium-carbon alloy.
 6. The junction field effecttransistor as in claim 1 wherein the gate electrode region comprises aplurality of silicon-germanium-carbon alloy layers.
 7. The junctionfield effect transistor as in claim 1 further comprises a gate contactregion formed on the third portion of the gate electrode region.
 8. Thejunction field effect transistor as in claim 1 further comprises: asource contact region formed on the source region; a drain contactregion formed on the drain region; and a well contact region formed onthe well region.
 9. The junction field effect transistor as in claim 8further comprises: a silicide layer overlaying a top surface of the gateelectrode region, a top surface of the source region, a top surface ofthe drain region, and a top surface of the well regions.
 10. Thejunction field effect transistor as in claim 8 farther comprises adielectric layer formed on top of the semiconductor substrate andoverlaying the source contact region, the drain contact region, the gateelectrode region, and the well contact region; wherein the sourcecontact region, the drain contact region, the gate electrode region, andthe well contact region are formed from a polycrystalline silicon layer;wherein the polycrystalline silicon layer is substantially planar;wherein the polycrystalline silicon layer is patterned and etched toform the source contact region, the drain contact region, the gateelectrode region, and the well contact region; and wherein thedielectric layer is patterned and etched to form contact holes withsubstantially the same depth to the source contact region, the draincontact region, the gate electrode region, and the well contact region.11. The junction field effect transistor as in claim 8; wherein thesource region comprises a first source region and a second sourceregion; wherein the first source region connects the second sourceregion and the channel region; wherein the impurity concentration of thefirst source region is controlled by a doping step independent of thesource contact region; wherein the second source region is formed onlyunderneath the source contact region; wherein the second source regionis not in contact with the channel region; wherein the second sourceregion has an impurity concentration doped from a source selected fromthe group consisting of the source contact region, an ion implantedregion, and a combination of the source contact region and an ionimplanted region; wherein the drain region comprises a first drainregion and a second drain region; wherein the first drain regionconnects the second drain region and the channel region; wherein theimpurity concentration of the first drain region is controlled by adoping step independent of the drain contact region wherein the seconddrain region is formed only underneath the drain contact region; whereinthe second drain region is not in contact with the channel region;wherein the second drain region has an impurity concentration doped froma source selected from the group consisting of the drain contact region,an ion implanted region, and a combination of the drain contact regionand an ion implanted region.
 12. The junction field effect transistor asin claim 11 wherein the separation distance between the second sourceregion and the channel region is independent of the separation distancebetween the second drain region and the channel region.
 13. A MOStransistor comprising: a semiconductor substrate of a first conductivitytype; a well region of a second conductivity type opposite to the firstconductivity type, formed in the semiconductor substrate and adjacent toa surface of the semiconductor substrate; an insulating region formed ofdielectric material in the semiconductor substrate and adjacent to thesurface of the semiconductor substrate; wherein the insulating regionsurrounds the well region; first and second non-overlapping regions ofthe first conductivity type formed in the well region and adjacent tothe surface of the semiconductor substrate; wherein the first and thesecond regions respectively form the source and drain regions of the MOStransistor; a gate dielectric layer formed of semiconductor oxide ornitrogenated oxide; formed immediately above the semiconductor substratebetween the source and drain regions; a gate region of the secondconductivity type comprising a first portion overlaying the gatedielectric layer; a second portion overlaying parts of the source anddrain regions; and a third portion overlaying parts of the insulatingregion; a source contact region formed on the source region; a draincontact region formed on the drain region; and a well contact regionformed on the well region; wherein the source region comprises a firstsource region and a second source region; wherein the first sourceregion connects the second source region and the region immediatelyunderneath the gate dielectric layer; wherein the impurity concentrationof the first source region is controlled by a doping step independent ofthe source contact region; wherein the second source region is formedonly underneath the source contact region; wherein the second sourceregion is not in contact with the region immediately underneath the gatedielectric layer; wherein the second source region has an impurityconcentration doped from a source selected from the group consisting ofthe source contact region, an ion implanted region, and a combination ofthe source contact region and an ion implanted region; wherein the drainregion comprises a first drain region and a second drain region; whereinthe first drain region connects the second drain region and the regionimmediately underneath the gate dielectric layer; wherein the impurityconcentration of the first drain region is controlled by a doping stepindependent of the drain contact region wherein the second drain regionis formed only underneath the drain contact region; wherein the seconddrain region is not in contact with the region immediately underneaththe gate dielectric layer; wherein the second drain region has animpurity concentration doped from a source selected from the groupconsisting of the drain contact region, an ion implanted region, and acombination of the drain contact region and an ion implanted region. 14.The MOS transistor as in claim 13 wherein the separation distancebetween the first source region and the region immediately underneaththe gate dielectric layer is independent of the separation distancebetween the first drain region and the region immediately underneath thegate dielectric layer.
 15. The MOS transistor as in claim 13 wherein thesemiconductor substrate comprises a material selected from a groupconsisting of silicon, germanium, silicon carbide, andsilicon-germanium-carbon alloy.
 16. The MOS transistor as in claim 13further comprises a dielectric layer formed on top of the semiconductorsubstrate and overlaying the source contact region, the drain contactregion, the gate region, and the well contact region; wherein the sourcecontact region, the drain contact region, the gate region and the wellcontact region are formed from a polycrystalline silicon layer; whereinthe polycrystalline silicon layer is substantially planar; wherein thepolycrystalline silicon layer is patterned and etched to form the sourcecontact region, the drain contact region, the gate region, and the wellcontact region; and wherein the dielectric layer is patterned and etchedto form contact holes with substantially the same depth to the sourcecontact region, the drain contact region, the gate region, and the wellcontact region.
 17. An electronic circuit comprising one or more deviceswherein at least one device in the electronic circuit comprises ajunction field effect transistor as in claim
 1. 18. An electroniccircuit as in claim 17 wherein at least one device in the electroniccircuit comprises a MOS transistor.
 19. An electronic circuit as inclaim 17 wherein at least one device in the electronic circuit comprisesa bipolar transistor.
 20. An electronic circuit comprising one or moredevices wherein at least one device in the electronic circuit comprisesa MOS transistor as in claim
 13. 21. An electronic circuit as in claim20 wherein at least one device in the electronic circuit comprises ajunction field effect transistor as in claim
 1. 22. An electroniccircuit as in claim 20 wherein at least one device in the electroniccircuit comprises a bipolar transistor.
 23. A method for fabricating oneor more semiconductor devices comprising the steps of: building one ormore isolation regions in a semiconductor substrate of a firstconductivity type, the isolation regions being filled with dielectricmaterial; doping one or more regions in the semiconductor substrate toform one or more well regions of the first conductivity type and one ormore well regions of the second conductivity type opposite to the firstconductivity type; forming one or more channel regions in the one ormore well regions wherein each channel region is of a conductivity typeopposite to the conductivity type of the corresponding well region;depositing a first semiconductor layer on the semiconductor substrate;doping the first semiconductor layer selectively above each well regionto dope one or more drain contact regions, one or more source contactregions, one or more gate electrode regions, and one or more wellcontact regions; wherein each drain and source regions are doped with aconductivity type opposite to the conductivity type of the correspondingwell region; wherein each gate electrode and well contact regions aredoped with the conductivity type of the corresponding well region;depositing a first dielectric layer on top of the first semiconductorlayer to form a blocking layer; masking and etching the firstsemiconductor layer for forming one or more drain contact regions, oneor more source contact regions, one or more gate electrode regions, andone or more well contact regions; forming one or more first source linkregions and one or more first drain link regions in the one or more wellregions by ion implantation; wherein each first source link regionconnects between a region immediately underneath a source contact regionand a channel region; wherein each first drain link region connectsbetween a region immediately underneath a drain contact region and achannel region; and wherein each first source link region and each firstdrain link region are implanted with a conductivity type opposite to theconductivity type of the corresponding well region; annealing thesemiconductor substrate with the first semiconductor layers and thefirst dielectric layer; filling up the regions etched away in the firstsemiconductor layer during the masking and etching step with dielectricmaterial for forming a planar surface; removing the blocking layernon-selectively; forming silicide on top of the first semiconductorlayer selectively; depositing a second dielectric layer on thesemiconductor substrate and etching to form contact holes; anddepositing and etching one or more metal layers on the semiconductorsubstrate for forming interconnections.
 24. The method as in claim 23wherein the annealing step comprises: forming a gate region underneatheach gate electrode region wherein the gate region has an impurityconcentration doped from the gate electrode region; forming a secondsource region underneath each source contact region wherein the secondsource region has an impurity concentration doped from the sourcecontact region; wherein the second source region connects with a firstsource region; and forming a second drain region underneath each draincontact region wherein the second drain region has an impurityconcentration doped from the drain contact region; wherein the seconddrain region connects with a first drain region.
 25. The method as inclaim 24; wherein the semiconductor substrate is made of silicon;wherein the first semiconductor layer is made of polycrystallinesilicon; and wherein the first dielectric layer is made of siliconnitride.
 26. The method as in claim 23 further comprises, after the stepof forming one or more channel regions, the steps of: forming a gatedielectric layer on top of the semiconductor substrate and selectivelyremoving the gate dielectric layer over a source region, a drain region,and a well region for forming an MOS transistor; and selectivelyremoving the gate dielectric layer over a channel region, a sourceregion, a drain region, and a well region for forming a junction fieldeffect transistor.
 27. A computer readable medium including one or moredata structures representing an electronic circuit: wherein at least onedata structure comprises a net-list; wherein at least one device in theelectronic circuit comprises a junction field effect transistor as inclaim
 1. 28. A computer readable medium including one or more datastructures representing an electronic circuit: wherein at least one datastructure comprises a member of a cell library; wherein at least onedevice in the electronic circuit comprises a junction field effecttransistor as in claim
 1. 29. The computer readable medium as in claim28 wherein the member of the cell library includes information relatingto timing, power, and size.
 30. A computer readable medium including oneor more data structures representing an electronic circuit: wherein atleast one data structure comprises a net-list; wherein at least onedevice in the electronic circuit comprises an MOS transistor as in claim13.
 31. A computer readable medium including one or more data structuresrepresenting an electronic circuit: wherein at least one data structurecomprises a member of a cell library; wherein at least one device in theelectronic circuit comprises an MOS transistor as in claim
 13. 32. Thecomputer readable medium as in claim 31 wherein the member of the celllibrary includes information relating to timing, power, and size.
 33. Acomputer readable medium including one or more data structuresrepresenting an electronic circuit: wherein at least one data structurecomprises a representation of a physical layout of the electroniccircuit; wherein at least one device in the electronic circuit comprisesa junction field effect transistor as in claim
 1. 34. The computerreadable medium as in claim 33 wherein at least one data structure is acell library.
 35. The computer readable medium as in claim 34 whereinthe cell library includes information relating to timing, power, andsize.
 36. A computer readable medium including one or more datastructures representing an electronic circuit: wherein at least one datastructure comprises a representation of a physical layout of theelectronic circuit; wherein at least one device in the electroniccircuit comprises an MOS transistor as in claim
 13. 37. The computerreadable medium as in claim 36 wherein at least one data structure is amember of a cell library.
 38. The computer readable medium as in claim37 wherein the cell library includes information relating to timing,power, and size.
 39. An electronic display for displaying a physicallayout of an electronic circuit wherein at least one device in theelectronic circuit comprises a junction field effect transistor as inclaim
 1. 40. An electronic display for displaying a physical layout ofan electronic circuit wherein at least one device in the electroniccircuit comprises an MOS transistor as in claim
 13. 41. A physicaldesign automation system for producing a physical layout of anelectronic circuit wherein at least one device in the electronic circuitcomprises a junction field effect transistor as in claim
 1. 42. Aphysical design automation system for producing a physical layout of anelectronic circuit wherein at least one device in the electronic circuitcomprises a MOS transistor as in claim
 13. 43. The physical designautomation system as in claim 41 wherein at least one junction fieldeffect transistor is an nJFET comprising a p-well contact region coupledto an external pad.
 44. The physical design automation system as inclaim 41 wherein at least one junction field effect transistor is apJFET comprising an n-well contact region coupled to an external pad.45. The electronic circuit as in claim 17: wherein at least one junctionfield effect transistor is an nJFET comprising a p-well contact regioncoupled to an external pad; wherein upon a bias voltage being applied tothe external pad a manufacturing defect causing leakage current can beidentified.
 46. The electronic circuit as in claim 17: wherein at leastone junction field effect transistor is a pJFET comprising an n-wellcontact region coupled to an external pad; wherein upon a bias voltagebeing applied to the external pad a manufacturing defect causing leakagecurrent can be identified.
 47. A method to design an electronic circuitcomprising the steps of: having at least one nJFET device in theelectronic circuit; having an external pad coupled to all nJFETs in theelectronic circuit; wherein upon the electronic circuit being fabricatedand a bias voltage being applied to the external pad a manufacturingdefect causing leakage current can be identified.
 48. A method to designan electronic circuit comprising the steps of: having at least one pJFETdevice in the electronic circuit; having an external pad coupled to allpJFETs in the electronic circuit; wherein upon the electronic circuitbeing fabricated and a bias voltage being applied to the external pad amanufacturing defect causing leakage current can be identified.
 49. Amethod to test an electronic circuit comprising the steps of:identifying at least one pJFET device in the electronic circuit;identifying an external pad coupled to all pJFETs in the electroniccircuit; applying a bias voltage to the external pad; determining amanufacturing defect causing leakage current.
 50. A method to test anelectronic circuit comprising the steps of: identifying at least onenJFET device in the electronic circuit; identifying an external padcoupled to all nJFETs in the electronic circuit; applying a bias voltageto the external pad; determining a manufacturing defect causing leakagecurrent.
 51. A junction field effect transistor with reduced capacitancecomprising a first gate circuit and a second circuit; wherein the firstgate circuit comprises a polysilicon gate electrode region and a gateregion; wherein the gate region is in proximity of the polysilicon gateelectrode region; and wherein the gate region comprises impurityconcentration doped from the polysilicon gate electrode region.
 52. AMOS transistor with reduced capacitance comprising a source, a drain, agate, a source link region and a drain link region; wherein the sourcelink region provides isolation between the source and the gate; whereinthe drain link region provides isolation between the drain and the gate;wherein the dimension of the source link region is independent of thedimension of the drain link region.
 53. An electronic circuit comprisingat least one nJFET and one pJFET fabricated using silicon or siliconalloys wherein gate leakage current is limited by limiting Vdd to lessthan built-in potential of a p-n junction in the silicon or siliconalloys.
 54. The electronic circuit as in claim 53 wherein minimumdimensions are 70 nanometers or less.
 55. An electronic circuitcomprising an nJFET and a pJFET; wherein a drain terminal of the nJFETis coupled to a drain terminal of the pJFET; wherein a gate terminal ofthe nJFET is coupled to a gate terminal of the pJFET; and wherein thenJFET and the pJFET operate in a complimentary mode.
 56. An electroniccircuit comprising a first circuit and a second circuit; wherein thefirst circuit comprises an nJFET and a pJFET; wherein the nJFET iscoupled to the pJFET for implementing a logic gate selected from thelist consisting of inverter, nand, nor, latch, flip-flop, counter,multiplexer, encoder, decoder, adder, multiplier, arithmetic logic unit,programmable logic cell, memory cell, micro-controller, JPEG decoder,and MPEG decoder.
 57. The electronic circuit as in claim 56 wherein thesecond circuit comprises an MOS transistor.
 58. The electronic circuitas in claim 56 wherein the second circuit comprises a bipolartransistor.
 59. A computer readable medium including one or more datastructures representing an electronic circuit: wherein at least one datastructure comprises a net-list; wherein the electronic circuit comprisesan nJFET and a pJFET; wherein a drain terminal of the nJFET is coupledto a drain terminal of the pJFET; wherein a gate terminal of the nJFETis coupled to a gate terminal of the pJFET; and wherein the nJFET andthe pJFET operate in a complimentary mode.
 60. The computer readablemedium as in claim 59 wherein the electronic circuit further comprisesan MOS transistor.
 61. The computer readable medium as in claim 59wherein the electronic circuit further comprises a bipolar transistor.62. A computer readable medium including one or more data structuresrepresenting an electronic circuit: wherein at least one data structurecomprises a member of a cell library; wherein the electronic circuitcomprises an nJFET and a pJFET; wherein a drain terminal of the nJFET iscoupled to a drain terminal of the pJFET; wherein a gate terminal of thenJFET is coupled to a gate terminal of the pJFET; and wherein the nJFETand the pJFET operate in a complimentary mode.
 63. The computer readablemedium as in claim 62 wherein the member of the cell library includesinformation relating to timing, power, and size.
 64. A computer readablemedium including one or more data structures representing an electroniccircuit: wherein at least one data structure comprises a representationof a physical layout of the electronic circuit; wherein the electroniccircuit comprises an nJFET and a pJFET; wherein a drain terminal of thenJFET is coupled to a drain terminal of the pJFET; wherein a gateterminal of the nJFET is coupled to a gate terminal of the pJFET; andwherein the nJFET and the pJFET operate in a complimentary mode.
 65. Anelectronic display for displaying a physical layout of an electroniccircuit: wherein the electronic circuit comprises an nJFET and a pJFET;wherein a drain terminal of the nJFET is coupled to a drain terminal ofthe pJFET; wherein a gate terminal of the nJFET is coupled to a gateterminal of the pJFET; and wherein the nJFET and the pJFET operate in acomplimentary mode.
 66. An physical design automation system forproducing a physical layout of an electronic circuit: wherein theelectronic circuit comprises an nJFET and a pJFET; wherein a drainterminal of the nJFET is coupled to a drain terminal of the pJFET;wherein a gate terminal of the nJFET is coupled to a gate terminal ofthe pJFET; and wherein the nJFET and the pJFET operate in acomplimentary mode.
 67. A method to design an electronic circuitcomprising the steps of: having at least one nJFET device and one pJFETdevice in the electronic circuit; coupling a drain terminal of the nJFETto a drain terminal of the pJFET; coupling a gate terminal of the nJFETto a gate terminal of the pJFET; wherein the nJFET and the pJFET operatein a complimentary mode; having at least one external pad coupled to atleast one net in the electronic circuit wherein upon the electroniccircuit being fabricated and a bias voltage being applied to the atleast one external pad a manufacturing defect causing leakage currentcan be identified.
 68. The junction field effect transistor as in claim7 wherein the dimension of the gate region is smaller than a minimumdimension of the gate contact region.
 69. The junction field effecttransistor as in claim 1 further comprises a gate contact region formedon the first portion of the gate electrode region.
 70. A junction fieldeffect transistor comprising a source region, a drain region, a gateregion, and a channel region; wherein the gate region is of alithographic minimum dimension; wherein length difference of the gateregion and the channel region is formed from lateral diffusion of thesource region and the drain region; and wherein lithographicmisalignment does not contribute to said length difference.
 71. Thejunction field effect transistor as in claim 9 wherein the silicidelayer overlaying a top surface of the gate electrode region, the gateelectrode region, the gate region, and the channel region havesubstantially the same length.
 72. The junction field effect transistoras in claim 9 further comprising a spacer layer formed of dielectricmaterial overlaying one or more sidewalls of the gate electrode region.73. The junction field effect transistor as in claim 1 wherein thesubstrate is of the first conductivity type.
 74. The junction fieldeffect transistor as in claim 1 wherein the substrate is of the secondconductivity type.
 75. The junction field effect transistor as in claim73 further comprises a second well region of the second conductivitytype formed in the semiconductor substrate and adjacent to the surfaceof the semiconductor substrate; wherein the well region of the firstconductivity type is formed within the second well region.
 76. Themethod as in claim 23 further comprising, between the masking andetching step and the forming one or more first source link regions andone or more first drain link regions step, a step of re-oxidizing thefirst semiconductor layer whereby the one or more semiconductor deviceis operable with reduced sidewall leakage current.
 77. The junctionfield effect transistor as in claim 2 wherein the channel region and thegate region are formed of a plurality of epitaxially deposited layers ofsilicon-germanium-carbon alloy of varying composition.
 78. The junctionfield effect transistor as in claim 3 wherein the epitaxially depositedsilicon-germanium-carbon alloy material are doped in-situ.
 79. Thejunction field effect transistor as in claim 10 wherein the gateelectrode region, the source contact region, the drain contact region,and the well contact region are substantially planar.